1. Field of the Invention
The invention relates generally to methods for the fabrication of integrated circuit devices and particularly to the controlled etch of vias in dielectric layers to form vias having straight sidewalls.
2. Discussion of the Prior Art
Computing technology has revolutionized the way people work and play and has contributed enormously to the advancement of humankind. Much of computing technology has been enabled by the discovery and advancement of semiconductor processing technology.
In the field of integrated circuit manufacturing, a fundamental goal is to design and manufacture integrated circuits to be as small as possible. As is well known in this art, the manufacturing cost of an integrated circuit corresponds strongly to the wafer area occupied by each integrated circuit die or chip. This is because the chip area correlates directly to the number of possible integrated circuits per manufactured wafer, and because the theoretical yield, for a given manufacturing defect density, increases as chip area decreases. In addition, the smaller feature sizes that result in decreasing chip area also provide improved device performance and increased functionality per unit area.
FIG. 1 shows a portion of an interconnect stack 10 before any etching has taken place but following litho-patterning as is known in the art. The interconnect stack 10 includes a substrate 12 which may be an interlayer dielectric (ILD) layer having Cu interconnects 16 formed therein. An etch stop layer 18 is formed over the substrate 12 and the Cu interconnects 16 and acts as a capping layer for the substrate 12 and Cu interconnects 16. FIG. 1 shows an oxide-like transition layer 24 formed over the etch stop layer 18. The oxide-like transition layer 24 promotes adhesion of the capping layer or etch stop 18, and an interlayer dielectric (ILD) 14 formed over the oxide-like transition layer 24. The use of the oxide-like transition layer is particularly useful when the ILD layer is formed of low-k or ultra low-k material. A hardmask 22 is formed on a second ILD layer 14. Finally, a photoresist 20 is formed on the hardmask 22.
The ILD layer 14 is preferably low or ultra low-k dielectric layers formed by chemical vapor deposition (CVD). The etch stop layer 18 prevents diffusion of Cu into the ILD 14 from the Cu interconnect as well as preventing diffusion to neighboring metal lines. For 90 nm via width and smaller technologies which use CVD low-k ILD, the etch stop layer 18 may be, for example, SiCN formed of either C-doped SiN or N-doped SiC, though other materials may also be used. The oxide-like transition layer is not necessary for all interconnects 10, but as will be explained below, is common for technologies using low-k or ultra low-k ILD layers.
Due to its relatively high k-value as compared to the ILD layer 14, the etch stop layer 18 is generally formed at less than 500 Å, and usually within the range of 250-400 Å, but technological development continues to reduce the low end of this range. One problem associated with the etch stop layer 18 is that, particularly when used in combination with low-k and lower-k CVD deposited ILD layers, it has poor etch selectivity. That is, it is difficult to critically control the etch process. Typical etch procedures use for example carbon-fluorine (CxFx) organic chemistries in varying concentrations to perform the etch process in a step-wise fashion. Often such an organic etch chemistry will have a higher CxFx concentrations in initial etching and have a lower concentration, producing less reactivity, for the subsequent etching steps, resulting in greater selectivity. Because such thin films of SiCN provide poor etch selectivity properties with respect to low-k or ultra low-k ILD layers, its use can lead to etch stop layer breakthrough during etching and/or over etch during the etching process. Because the via walls become tapered during these process steps, other problems can result such as high via resistance, large via resistance variation between successive vias, and ultimately via failure. During the etching process the CxFx etching materials are absorbed into the porous ILD layers, as a result during subsequent ashing procedures using oxygenated ashing materials, the residual CxFx is released causing further detrimental etching. Often this additional etching during the ashing process results in the formation of a taper at the bottom of the via 26 in the etch stop layer 18. This etching caused by the release of CxFx from the ILD layer is called the “Memory Effect.”
The use of ultra low-k ILD layers (k≦2.5), for example in new technology such as 45 nm Back-End-of-Line (BEOL) platforms, where for example the gate width is a mere 45 nm, creates new issues to overcome. An ultra low-k ILD layer 14 does not adhere well to the SiCN due to chemistry differences (organic vs. inorganic) and the fact that ultra low-k ILD is porous, thus reducing the surface area for adequate adhesion. Because an ultra low-k ILD layer 14 does not adhere well to the SiCN etch stop layer 18, an oxide-like transition layer 24 is used between the etch stop and the ILD layer 14 to promote adhesion and structural integrity. While the oxide-like transition layer 24 promotes good adhesion, it exacerbates the problems with etching and etch process selectivity and the formation of tapering at the bottom of the vias. This is demonstrated in FIGS. 2a and 2b. 
The oxide-like transition layer 24 has a different etch rate than the SiCN etch stop layer 18 and the ILD layer 14. It is normally etches slower that the ILD layer 14. This slower etching makes the tapering experienced at the bottom of the via 26 worse than if the transition layer 24 were not there. Further, as can be seen by the comparison of FIGS. 2a and 2b, following subsequent resist stripping via the ashing process, again residual CxFx causes further memory effect etching, and actually increases the taper problems experienced. As discussed above, this tapering results in high via resistance, large via resistance variation between successive vias, and ultimately via failure.
Accordingly, there is a need for an integrated circuit having straight sided vias, to increase the uniformity of the via resistance, particularly in devices using ultra low-k ILD layers requiring the use of an oxide like transition layer for proper adhesion of the ILD, Cu interconnect, and the SiCN etch stop layer. The present invention is directed to providing such a method and circuit.